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SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language Features

SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language Features at Amazon.com


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ISBN: 0387765298 - SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language Features  
Title:SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language Features
Author:Chris Spear
Publisher:Springer
Type:Book / Hardcover
Publication Date:05 June, 2008
ISBN / ISBN-13:0387765298  /  9780387765297
List Price:$135.00
You Save:$27.12
Amazon Price:$107.88

* This book is also available, brand-new, from 3rd-party marketplace sellers at Amazon.com, from $98.34.



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Editorial Review / Publisher's Information:

Product Description

SystemVerilog for Verification, Second Edition provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types.

This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch. This edition also includes a new chapter that covers “Interfacing to C” and many new and improved examples and explanations.

For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

"The complete book that covers verification concepts and use of system verilog in Verification, taking your from an easy start to advanced concepts with ease.

Paul D. Franzon, Alumni Distinguished Professor of ECE, North Carolina State University"



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Customer Reviews:

 • Good Introduction -- 3 And Half Stars
10 January, 2007

Book is a good introduction to system verilog for verification - though some typographical mistakes and some coding mistakes, make it bit flaky. I would definately recommend this book - as it is the fastest way to get going around system verilog. One thing I like is that it is tied to any vendor specific methodology like RVM or AVM or VMM.

- Reviewed by customer ID: A29XS2UNTOSUNN

 • Excellent Starter Book For Newbies
03 November, 2008

I purchased this book since I had to implement a new verification environment from scratch. I read the entire book, and I was off building a verification environment with SV. There are few details which are not discussed in the book, for instance how to import classes into other classes(from a package), and how you should compile the entire project (again from a package). Overall, if you don't know SV, and OOP, this is an excellent book to start with.

- Reviewed by customer ID: A3OYKAGFPLP5FP

 • Excellent Book For Systemverilog Newbie
10 December, 2008

This is an excellent systemVerilog introduction book, if you are experienced verilog user want to learn systemVerilog, this book is the right one for you. Highly recommend to anyone who want to utilize systemVerilog features to enhance their current verification environment.

- Reviewed by customer ID: AG8W9U3WE7F8D

 • Excellent Book Except For ...
16 January, 2007

a few non-compliant code examples that do not follow the IEEE LRM. With that said, overall the book contains a number of good examples and covers the SV language. It doesn't spend much time discussing methodology (which can be good or bad depending on what you're looking for). In summary, decent reading and a good language reference. Definitely a lot better than the VMM book.

- Reviewed by customer ID: A2LAFV10NKDZFG

 • Systemverilog
10 January, 2007

Helpful for those migrating from verilog because it compares the new concepts in relation to known concepts of verilog. I liked the "bug" symbol that cautions against possible coding problems. All systemverilog concepts are covered in the book with examples. What is lacking is a practical usable example to build a complete simulation environment.

- Reviewed by customer ID: A27CV8PD09Z4OL


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