Verilog HDL Synthesis, A Practical Primer | 
|  | | | Title: | Verilog HDL Synthesis, A Practical Primer | | Author: | J. Bhasker | | Publisher: | Star Galaxy Pub | | Type: | Book / Paperback | | Publication Date: | October, 1998 | | ISBN / ISBN-13: | 0965039153 / 9780965039154 | | List Price: | $69.95 | | You Save: | $1.40 | | Amazon Price: | $68.55 | |
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Product Description
With this book, you can: - Start writing synthesizable Verilog models quickly. - See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic. - Learn techniques to help avoid having functional mismatches. - Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.
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Customer Reviews:
• Best Verilog Synthsis Book 27 July, 2001
This is the best book about the Verilog Synthesis. The book is very practical, and I immediately applied many examples into my work....
- Reviewed by customer ID: A2CZLAPBA6QQU2
• Great Verilog Info For Synthesis 13 September, 2000
This book is an excellant reference for anyone writing Verilog for synthesis. I found the examples useful and complete.
- Reviewed by customer ID: A1PJ9ZE6ZTMLK8
• This Is A Very Good (and Short) Book On Verilog Synthesis 17 November, 2001
The author does a very good job of covering synthesizable Verilog. The numerous examples provide the reader with solid Verilog coding style guidelines. In addition, the author's discussion of blocking and non-blocking assignment statements for synthesizing combinational and sequential logic is very clear and concise. The only complaint I have about the book is its weak treatment of parameterizable design for synthesis. Despite the drawback, this is a very good reference and coding style guide for writing synthesizable Verilog.
- Reviewed by customer ID: A85CD1KWGHCS8
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